The silicon wafers used for very large scale integration (VLSI) circuits are ideally flat. However, after many process steps, such as growth or deposition of various insulating and conductive layers, a nonplanar structure is usually formed. For example, the gate oxide of a metal oxide semiconductor (MOS) transistor is only 100-250 angstroms thick, whereas the field oxide may be 10000 angstroms thick. The nonplanarity primarily results in two problems. The first is the difficulty of maintaining step coverage without breaks in the continuity of fine lines. The second is the inability to lithographically transfer fine-line patterns to the wafer.
More specifically, lithography technique has steadily shifted towards shorter wavelengths, such as the deep ultraviolet (DUV), in order to reduce the minimum feature size. Unfortunately, decreasing the wavelength results in reducing the depth of focus (DOF), which is an important parameter because the surface of the microcircuit has a nonplanar topographical surface. Therefore, the number of photolithography steps required to cover the microcircuit is increased, thereby increasing the time required to fabricate the microcircuit.
Techniques for planarization are, therefore, become more important. Borophosphosilicate glass (BPSG) deposited by using ozone-tetraethylorthosilane (TEOS) or low pressure TEOS (LPTEOS) has been conventionally used as an interpoly oxide (IPO) layer in order to planarize interpoly layers. Unfortunately, the BPSG layer usually results in an autodoping effect, in which the boron ions contained in the BPSG diffuse down to the underlying polysilicon, thereby altering the concentration profile therein. Furthermore, the temperature in densifying the BPSG layer thus deposited is very high, usually higher than 850 .degree. C., resulting in a high thermal budget.